1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a single-chip integrated semiconductor device including a vertical power MOSFET used such as a high-side switch and a CMOS circuit used such as a peripheral circuit therefor.
2. Description of the Background Art
Recently, a single-chip integrated semiconductor device (power IC) including a vertical power MOSFET (VDMOS) used as a switching device for a variety of power loads on an automobile, and CMOS peripheral circuits for the VDMOS, has been proposed. In such a power IC, a self-isolation technique having a relatively simple manufacturing process is advantageously employed for cost reduction, and thus the VDMOS is used as a high-side switch which drives the load in its source-follower circuits.
In FIG. 1, there is shown a conventional power IC for automotive use, as disclosed in IEEE International Solid-State Circuits Conference, 1986, p22. As shown in FIG. 1, in an N.sup.+ -type semiconductor substrate 61, an N.sup.+ -type epitaxial layer 62 is grown on its upper surface portion, and some elements or devices for constituting the power IC are formed in the upper surface area of the epitaxial layer 62, as follows.
In the N.sup.- -type epitaxial layer 62, a P-type channel region 63 is formed in the upper surface area, and a VDMOS 64 is formed in the channel region 63 while the epitaxial layer 62 is used as a substantial drain region. A power or battery voltage Vbat is applied to a drain electrode 65 attached to the rear surface of the N.sup.+ -type substrate 61. Further, a low voltage P-channel MOSFET (LVPMOS) 66 with a low breakdown voltage and a high voltage P-channel MOSFET (HVPMOS) 67 with a high breakdown voltage are directly formed in the epitaxial layer 62. Two P-type well regions 68 and 69 are formed in the surface area of the epitaxial layer 62 by an impurity doping technique, and a low voltage N-channel MOSFET (LVNMOS) 71 with a low breakdown voltage and a high voltage N-channel MOSFET (HVNMOS) 72 with a high breakdown voltage are formed in the P-type well regions 68 and 69, respectively.
In the power IC shown in FIG. 1, by applying the battery voltage Vbat to the electrode 65, the N.sup.+ -type substrate 61 and the N.sup.- -type epitaxial layer 62 are maintained to the maximum voltage in the device, and each PN junction between the N.sup.- -type epitaxial layer 62 and the P-type regions formed in the N.sup.- -type epitaxial layer 62 of each device is reverse-biased by the maximum voltage. Hence, the devices can be electrically isolated from one another, and be independently operated.
In FIG. 2, there is shown an equivalent circuit of the power IC of FIG. 1. A high voltage CMOS (HVCMOS) circuit 73 includes at least the HVPMOS 67 and the HVNMOS 72, and a low voltage CMOS (LVCMOS) circuit 74 includes at least the LVPMOS 66 and the LVNMOS 71. The LVCMOS circuit 74 may be operated by a voltage Vreg such as 5V fed from an electric power supply contained in the power IC, as hereinafter described in detail, and a load 75 is connected between the source electrode 76 of the VDMOS 64 and the ground GND.
In FIG. 3, there is shown a load driver using the power IC described above, including an electric power supply 77 for obtaining the voltage Vreg, a first protector 78 for preventing an overcurrent, an excessive temperature and the like, a second protector 79 for preventing an overvoltage and the like. The load driver further includes a charge pump (gate booster) 81 for preventing the increase of the power loss due to an on-resistance increase. That is, when no charge pump 81 is provided, the essential gatesource voltage is lowered by the source voltage increase of the VDMOS 64 during its conducting operation. In this case, the HVCMOS circuit 73 is used as a level shifter 80 to which a high voltage is applied, and the other logical circuits are comprised of the LVCMOS circuit 74.
The battery voltage Vbat is, for example, approximately 12 to 16V for the automobile, and the voltage Vreg to be applied to the LVCMOS circuit 74 is determined to, for instance, 5V by the power supply 77. Thus, the LVNMOS 71 is required a withstanding voltage higher than the determined voltage Vreg, and, since the LVPMOS 66 is directly formed in the N.sup.- -type epitaxial layer 62 to which the power voltage Vbat is applied, its withstanding voltage higher than the power voltage Vbat is required.
When the power IC is employed for the driver of the loads on the automobile, the power voltage Vbat may be varied from approximately 6V when cranking, to approximately 60V on an unusual operation such as a load dump. Hence, in the devices formed in the epitaxial layer 62 to which the power voltage Vbat is applied, a withstanding voltage of every PN junction formed between the N.sup.- -type epitaxial layer 62 and a P-type region of each device therein is determined to be greater than 60V.
Since the LVNMOS 71 is separated from the epitaxial layer 62 by the P-type well region 68, there is no need to make the LVNMOS 71 to a high voltage structure such as LDD. On the other hand, since the LVPMOS 66 is directly formed in the N.sup.- -type epitaxial layer 62, its isolation withstanding voltage is required to be determined greater than 60V even when its power source line is set to, for instance, 5V regulated by the power supply 77. In order to obtain such a high voltage isolation structure, it is necessary to supplementarily provide a lightly doped source (LDS) 83 and a lightly doped drain (LDD) 85 instead of a conventional highly doped single drain structure and approximately several .mu.m of the diffusion depth XJ is required. Thus, in this case, it is difficult to miniaturize the devices, and the areas of the devices become large even when a channel length L of the MOSFET, as shown in FIG. 4, is reduced. Hence, in the power IC chip, as the LVCMOS circuit 74 occupying a large area, the chip size becomes large with a cost increase.
As shown in FIG. 2, in the LVCMOS circuit 74, the the substrate voltage of the LVPMOS 66 is Vbat, and its source voltage is Vreg fed from the power supply 77. Accordingly, a voltage difference Vbat-Vreg arises between the substrate and the source in the LVPMOS 66, and its gate threshold voltage Vth is raised by the substrate bias effect. In the automobile, since the variation of the power voltage Vbat is large, the gate threshold voltage vth in the LVPMOS 66 also varies corresponding thereto, and thus the margin of the LVCMOS circuit 74 is narrowed.